Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 371

The pin is used as the strap option for the selection. If the
BMS
sampled high during reset, this causes the processor to go into idle and
disables master mode boot DMA. When the processor is in idle state wait-
ing for a host or link boot, any signal from the host or link causes a slave
mode boot.
Any link port can be used for booting, since all link ports are active and
waiting to receive data upon power up reset or after a hard reset. Link port
boot uses TigerSHARC processor's link port DMA channels. All link port
DMAs are initialized to transfer 256 words to TigerSHARC processor's
internal memory block 0, locations 0x00-0xFF. An interrupt occurs at the
completion of the DMA transfer and the TigerSHARC processor starts
executing the boot loader kernel at internal memory location 0x0. It is
intended that these first 256 words act as a boot loader to initialize the rest
of TigerSHARC processor internal memory. The boot loader kernel then
brings in the application code and data through a series of single-word
DMA transfers. Finally, the boot loader kernel overwrites itself with the
application code, leaving no trace of itself in TigerSHARC processor
internal memory.
When this series of DMA processes completes, the IVT entry of the link
port DMA channel points to internal memory address 0, allowing the
user's application code to begin execution. Analog Devices supplies a
default link port boot loader kernel, (
alDSP++ software development tools.
The default link port loader kernel provided by Analog Devices within the
VisualDSP++ software development tools uses link port #3 to perform
link port booting. If another link port is required for booting the Tiger-
SHARC processor, the boot loader kernel source code can be modified
and rebuilt by the user to use any of the four link ports of the Tiger-
SHARC processor. For additional information, refer to the
Engineer-to-Engineer Note EE-174: ADSP-TS101 Boot Loader Kernels
Operation.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
), with the Visu-
TS101_link.asm
System Design
pin is
BMS
10-25