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Register Access Features
SUMEN Sum enable
CCYCLE User clock cycles
ISL Aborted instruction lines
BTBPR BTB predictions
SCYCLE Stall cycles
VBT Virtual bus transactions
MODULE Executed instructions
by modules
Bit21 – J-IALU
Bit22 – K-IALU
Bit23 – Compute block X
Bit24 – Compute block Y
Bit25 – Control flow instruction
1
BUS2
Transaction types
Bit18 – Single-word
Bit19 – Long-word
Bit20 – Quad-word
1
BUS1
Transaction types
Figure 2-2. PRFM (Upper) Register Bit Descriptions
1 Monitoring is performed on transactions driven on bus n (n is 0, 1, or 2), including virtual bus trans-
actions
2-24
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
continued on Figure 2-3
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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