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Pipelined Protocol
For pipelined protocol setup, the slow protocol bit is cleared and the pipe-
line depth field is set to the required pipeline depth (
for two cycles,
0b01
defines the pipeline depth for read transactions only; pipeline depth for
write transactions is always one. The
slaves in the address range of this bank, in order to prevent contention on
the data bus on transitions between different slaves on consecutive reads.
If this bank contains a single slave, the
internal wait field is irrelevant for pipelined transactions. In pipelined pro-
tocol, there is no internal wait state programming.
Initial Value
The initial value after reset, which can be used as the default, is as follows.
• Bus width: 32 for host, multiprocessing and memory access
• Bus configuration: slow protocol with three wait states
TigerSHARC Pipelined Interface
The TigerSHARC processor uses the pipelined protocol to interface with
other TigerSHARC processors, the host, and fast synchronous memories.
The transaction is also performed by the pipelined protocol when the Tig-
erSHARC processor is accessed as a slave.
This protocol was created for pipelining the transactions with a through-
put of one datum per cycle, although the latency of the transaction can be
up to four cycles. The address and controls of a transaction are issued on
the address cycle and the data is transferred a few cycles later—in the case
of TigerSHARC processor, one to four cycles depending on the transac-
tion direction and system configuration programming. The TigerSHARC
ADSP-TS101 TigerSHARC Processor
Hardware Reference
for three cycles, and
0b10
IDLE
0b00
for four cycles). This
0b11
bit is set if there are multiple
bit should be cleared. The
IDLE
Cluster Bus
for one cycle,
5-15
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