Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 187

SCLK
PI PE LEVEL 1
ADDR
AA0 AA 1
DATA DA0
WR
RD
BRST
ACK
Figure 5-23. Write to Host Transaction Followed by a Read Cycle From
the Host by the TigerSHARC Processor, Bus Width = 32
When the host accesses a TigerSHARC processor, it should comply with
all the rules of TigerSHARC processor pipelined transactions. The most
important rules are:
• Pipeline depth is always four for read and one for write.
• There are IDLE cycle restrictions.
• No read from broadcast address space is allowed.
• The host must operate with an identical system configuration as
other TigerSHARC processors on the cluster bus.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
HA0
AA2 A A3
QUAD-WORD
DA1 DA2 DA3
HO ST PIPE LEVEL 2
HA1
LONG_WORD
HD0 HD1
Cluster Bus
PIPE LEVEL 1
AB2
A B0 AB1
QUAD-WORD
DB0 DB1
5-49