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S
S unit, See shifter
Scalability and Multiprocessing
1-18
scalability and multiprocessing
1-24
SCLK (System Clock) 1-23, 3-1,
3-10, 5-47
SDRAM 2-2, 2-36, 2-41, 4-8, 5-2,
6-1, 6-2, 6-7, 6-9, 6-10, 6-34, 6-38,
6-42
Precharge-to-RAS delay 6-2
RAS-to-Precharge delay 6-2,
6-35
refresh 5-1, 6-3, 6-43
refresh rate 6-3
SDRAM A10 (SDA10) 6-8,
6-9, 6-10, 6-13, 6-14,
6-15, 6-16, 6-17, 6-18
SDRAM Clock Enable (SD-
CKE) 6-8, 6-10, 6-38,
6-43
SDRAM controller 5-1
SDRAM I/O pins 6-7–6-8
SDRAM interface 5-3, 6-1,
6-43
SDRAM physical connection
6-11–6-18
SDRAM programming 6-43
SDRAM protocol 2-4, 5-1,
5-34
SDRAM Write Enable (SD-
WE) 6-8, 6-9, 6-34
SDRAM
Control
ADSP-TS101 TigerSHARC Processor
Hardware Reference
(SDRCON) 6-19
SDRAM Controller Commands
6-30
SDRAM Controller Setup for AD-
SP-TS101S EZ-Kit Lite 6-44
SDRAM Enable - Bit0 6-22
SDRAM I/O Pins 6-7
SDRAM I/O Pins 6-7
SDRAM Interface 6-1
SDRAM Interface Throughput
6-27
SDRAM Physical Connection 6-8
SDRAM Programming 6-19
SDRAM programming 5-50
SDRCON (SDRAM Configura-
tion) (DMA 0x180484) 2-36
SDRCON SDRAM Configuration
Register 2-36, 2-41, 5-2, 6-1, 6-2,
6-10, 6-42
SDWE see SDRAM
Selecting the Booting Mode 10-18
selecting the booting mode 10-18
Selecting the CAS Latency Value
(CL) – Bits2-1 6-22
Selecting the Precharge to RAS
Delay (tRP) – Bits10-9 6-25
Selecting the RAS to Precharge
Delay (tRAS) – Bits13-11 6-26
Selecting the SDRAM's Page Size
(Page Boundary) – Bits5-4 6-25
Self-Refresh (SREF) Command
6-42
semaphores 1-20, 5-47, 5-51, 7-59
sequencer 1-13
Register
INDEX
xvii
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