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Interrupt Service
While preserving the current machine status in a stack, the appropriate
global interrupt enable bit (hardware or software) is still clear, so there is
no danger of corrupting the return address PC (
interrupt was a hardware interrupt, software or emulation exceptions can
still be processed, since the return address is saved in a different register
(
or
). This also applies to emulation exceptions when a software
RETS
DBGE
interrupt is executing its initial cycles.
Once the relevant registers are saved in memory, the return register should
be saved and the global interrupt disable bit
operation is performed automatically by saving the return address alias
.
RETIB
If the system does not need to support nested hardware interrupts, there is
no need to preserve the machine state in a stack. The return can be exe-
cuted from the
bit should be left as is. However, software interrupts or debug interrupts
may be nested. In these cases, the machine state should be retained before
software/debug service is performed.
The example below initializes the two timers and sets up their interrupts.
The lower priority interrupt allows nesting, the higher one does not need
to allow nesting.
.section data;
.var register_store;
store registers used in ISR*/
.var register_store_2;
.section program;
interrupts using the two timers.*/
Setup_Timer_Interrupts:
/*Set up the interrupt service routines in the Interrupt Vector
Table*/
4-20
register, and the hardware interrupt's global disable
RETI
/*internal memory location used to
/*This example shows how to set up nested
). If, however, the
RETI
should be set. This
PMASK60
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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