Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 408

INDEX
Transmitting and Receiving Data
8-4
TRAP instruction
Trap) 4-9
tRAS see Activ-to-Pre
(tRAS)
tRP see Pre-to-Activ delay (tRP)
turbo-code algorithms 1-9
Two-Dimensional DMA 7-10
Two-dimensional DMA 7-45
two-dimensional DMA 7-10, 7-17,
7-22, 7-28, 7-32, 7-36, 7-45–7-47,
7-51, 7-52, 7-53, 7-54, 7-55, 7-56,
7-57, 7-58, 7-59, 7-60, 7-64, 7-65,
7-66, 10-34, 10-35, 10-36, 10-37
Two-dimensional DMA Channel
Organization 7-45
Two-dimensional DMA Operation
7-46
Type Setup — AutoDMA (Chan-
nels 12, 13) 7-30
Type Setup — EP (Channels 0 to
3) 7-30
Type Setup — Links Receive
(Channels 8 to 11) 7-29
Type Setup — Links Transmit
(Channels 4 to 7) 7-29
U
Understanding DQM Operation
6-29
Unmapped Compute Block Regis-
ters 2-12
Ureg (Universal Register)
xx
(Supervisor
delay
ADSP-TS101 TigerSHARC Processor
see register
User Mode 3-5
V
Valid Width Settings 5-14
Vector Interrupt (VIRPT) 4-7
Vector Interrupt register see regis-
ter
VIRPT register (Vector Interrupt
register) see register
VisualDSP++ and Tools Manuals
-xxv
VisualDSP++ and tools manuals
-xxv
Viterbi algorithm 1-9
W
Wait Cycles 5-23
watchpoint 2-22, 2-25, 2-27, 3-3,
4-9, 9-2, 9-3–9-10
watchpoint control
(WPiCTL) 2-25, 9-4–
9-7
watchpoint status
(WPiSTAT) 2-27, 9-8
Watchpoint Address Pointers –
WP0L, WP1L, WP2L, WP0H,
WP1H and WP2H 2-29
Watchpoint Control – WP0CTL,
WP1CTL and WP2CTL 2-25
Watchpoint Operation 9-7
Watchpoint Status – WP0STAT,
WP1STAT and WP2STAT 2-27
Watchpoint Status (WPiSTAT)
Hardware Reference
register
register