Register Access Features
Some of the registers do not use all 32 bits. The unimplemented bits are
reserved, and should not be used. When writing to such a register, they
must be set to zero. When reading such a register, the unimplemented bits
may be of any value.
The register groups are:
•
–
0x00
0x09
•
–
0x0C
0x0F
•
,
0x1A
0x38
•
–
0x30
0x37
•
,
0x1B
0x3D
•
,
0x24
3A
•
–
0x20
0x23
•
–
0x25
0x27
• Others – Reserved. These registers must not be accessed by applica-
tions since they could cause unexpected behavior by the
TigerSHARC processor.
The register groups are described in the following sections.
Compute Block Register Files
The compute block register file is a 32-word register. There are two such
register files, one in each of the compute blocks (X and Y). The register
file is aliased in several groups, some of which are applicable for data trans-
fer instructions only. Some groups point to compute block X and some to
block Y; those that point to both compute blocks in parallel actually point
to the same register.
2-10
Compute block register file different aliases
Integer ALU registers
–
Interrupt and sequencer registers
0x39
,
Branch Target Buffer (
3B
,
,
Debug logic (0x3F reserved)
0x3E
0x3F
EP Control/Status registers
DMA registers
Link registers
) registers
BTB
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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