Slow Device Protocol
signal. One of the key requirements for this device is that it meets the hold
time for both address and data. The right number of wait cycles to guaran-
tee enough data setup time is user configurable.
0 WAIT
SCLK
ADDR
DATA
MS1-0
WR
ACK
Figure 5-11. Slow Protocol Write With 0 Wait Cycles
5-28
DATA
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Need help?
Do you have a question about the ADSP-TS101 TigerSHARC and is the answer not in the manual?
Questions and answers