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5-39, 5-40, 5-41, 5-50–5-51, 7-36
Bus Arbitration Protocol 5-41
bus arbitration protocol 5-41–5-43
Bus Control/Status (BIU) Register
Group 2-30
Bus Fairness — BMAX 5-47
Bus Interface I/O Pins 5-3
bus interface I/O pins 5-3–5-5
Bus Interface I/O Pins (Cont'd) 5-4
Bus Interface Unit 2-30, 3-4, 5-2
Bus Lock 5-47
bus lock 1-20, 2-21, 2-38, 2-41,
3-7, 3-8, 4-7, 5-39, 5-41, 5-47,
5-48, 5-51
Bus Lock Interrupt 4-7
Bus Lock Interrupt register see
register
Bus Master (BM) 4-6, 5-39
Bus Width 5-14
bus width 5-2, 5-14, 5-15, 5-16,
5-17, 5-35, 5-36, 6-36, 6-37, 6-40,
6-41
Bus Width = 32 6-37, 6-41
Bus Width = 64 6-36, 6-40
BUSLK System Control 2-38
BUSLK System Control Register
(bus lock) 2-38, 2-41, 3-7, 5-47,
5-48
BUSLOCK pin see bus lock
C
CAS Before RAS 6-42
see also SDRAM
refresh
ADSP-TS101 TigerSHARC Processor
Hardware Reference
CAS latency 5-36, 6-2, 6-35, 6-36,
6-37, 6-38, 6-40, 6-41
CBR see CAS Before RAS
CCLK (Internal Clock) 3-2, 5-47
Chain Insertion 7-44
Chained DMA 7-11
Clock Description and Jitter 10-15
Clock Distribution 10-15
Clock Domains 1-23
clock signal traces 10-15
Clocking 3-1
CLU 1-9
Cluster Bus 5-1
Cluster Bus Transfers 7-7
Column Address Strobe (CAS)
5-1, 6-2, 6-7, 6-9, 6-34, 6-38
COM port, McBSP, See link ports
Communications Logic Unit Reg-
isters 2-13
complex numbers 1-11
compute block 1-8
Compute Block Register Files
2-10
compute block register files 2-10–
2-14
ALU registers 2-13
broadcast transfer 2-11–2-12
compute block status registers
2-13
merged access 2-11
multiplier registers 2-13
shifter registers 2-13
unmapped compute block reg-
isters 2-12
INDEX
iii
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