Table of Contents
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Refresh (REF) Command ...................................................... 6-42
Self-Refresh (SREF) Command ............................................. 6-42
Programming Example ................................................................ 6-43
DIRECT MEMORY ACCESS
DMA Controller Features ............................................................. 7-7
Cluster Bus Transfers ............................................................... 7-7
AutoDMA Transfers ................................................................ 7-9
Link Transfers ......................................................................... 7-9
Two-Dimensional DMA ........................................................ 7-10
Chained DMA ...................................................................... 7-11
DMA Architecture ...................................................................... 7-11
DMAR I/O Pins ................................................................... 7-12
Terminology ......................................................................... 7-13
Setting Up DMA Transfers ......................................................... 7-14
DMA Transfer Control Block Registers ....................................... 7-15
DMA Channel Control ......................................................... 7-15
Transfer Control Block (TCB) Registers ............................ 7-15
DIx Register ................................................................. 7-16
DXx Register ................................................................ 7-17
DYx Register ................................................................ 7-17
DPx Register ................................................................ 7-18
DMA Control and Status Registers ............................................. 7-23
DMA Status Register (DSTAT/DSTATC) .............................. 7-23
DMA Control Registers ........................................................ 7-26
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ADSP-TS101 TigerSHARC Processor
Hardware Reference
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