Sdram Programming - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

SDRAM Programming

SDRAM Control Register (SDRCON)
SDRAMs are available from several vendors. Each vendor has different
SDRAM product requirements for the power up sequence and the timing
parameters—t
RAS
command delay). Use only SDRAMS that comply with Joint Electronic
Device Engineering Council (JEDEC) specifications. In order to support
multiple vendors, the TigerSHARC processor
grammed to meet these requirements.
Figure 6-4 on page 6-20 and Figure 6-5 on page 6-21 show the SDRAM
control register.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
( to command delay), t
ACT PRE
SDRAM Interface
and t ( to
PRE
RCD RP
register can be pro-
SDRCON
ACT
6-19