Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 231

Bus Width = 32
For the sequence in Figure 6-10, the following is true:
• latency = 2
CAS
• Bus width = 32
SCLK
SDCKE
MSSD
RAS
CAS
SDWE
RA1
A11-0
DATA31-0
DQ M
Figure 6-10. Bus Width = 32
(Burst Write Followed by Burst Write in the Same Page)
ADSP-TS101 TigerSHARC Processor
Hardware Reference
CA1
QUAD-WORD
DA1 DA2 DA3 DA4
SDRAM Interface
CB1
QUAD-WORD
DB4
DB1 DB2 DB3
6-41