Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 143

Table 5-1. Bus Interface I/O Pins (Cont'd)
Signal Description
Boot Memory Select
BMS
serves as chip select for boot EPROM or flash memory. If the TigerSHARC pro-
BMS
cessor is configured to boot from EPROM,
multiprocessor system,
a strap pin for EPROM boot mode.
Memory Select
MS1-0
or
MS0
or 1 respectively.
address pins during memory accesses.
In multiprocessing systems,
Memory Select Host
MSH
is asserted whenever the TigerSHARC processor accesses the host address space.
MSH
The
MSH
pins. In a multiprocessing system,
Flyby
FLYBY
When a TigerSHARC processor DMA channel is initiated in flyby mode, it generates
flyby transactions on the external bus. During flyby transactions, the
asserted, indicating the source or destination I/O device where the next data should be
placed, or where to strobe the current data. This event also signals that the system
should be ready for the next data on the next cycle.
I/O device Output Enable
IOEN
enables the output buffer of I/O device in flyby transactions from I/O to Mem-
IOEN
ory. Active on flyby transactions.
Burst
BRST
is asserted by the current bus master (TigerSHARC processor or a host) to indi-
BRST
cate data associated with consecutive addresses is being read or written. A slave device
may ignore addresses after the first one and increment an internal address counter after
each transfer. If the burst access is from the host to the TigerSHARC processor, the
TigerSHARC processor increments the address automatically as long as
asserted.
where the arbitration between multiple TigerSHARC processors and
between TigerSHARC processors and the host is accomplished using a
distributed arbitration logic on the TigerSHARC processors themselves.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
is driven by the bus master. During reset, the
BMS
is asserted whenever the TigerSHARC processor accesses memory banks 0
MS1
are decoded memory address pins changing concurrently with
MS1-0
MS1-0
pin is a decoded memory address pin changing concurrently with address
is active during the boot sequence. In a
BMS
are driven by the master.
is driven by the master.
MSH
Cluster Bus
is used as
BMS
pin is
FLYBY
is
BRST
5-5