External Port Dma - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

External Port DMA

External Port DMA
Four DMA channels define internal/external memory transfers, where
each channel has two
must be the same. These registers define the following.
• A channel is enabled if both
not set to 000.
• A channel's priority is high if the
and
TCBx
• DMA interrupt is enabled if the
TCBx DP
• DMA request mode is enabled if the
the
TCBx DP
• Internal and external memory transfer is set up in the
the
TCBx
between the TigerSHARC processor's internal memory and exter-
nal memory or devices.
The field must point to the operating channel in both
CHTG
ters if chaining is enabled—for example, in
must be 1 in both
respective
CHPT
Internal and External Address Generation
DMA transfers between the TigerSHARC processor internal memory and
external memory require the DMA controller to generate addresses for
both. The external address is generated according to the information in
the external memory
page 7-15.) The internal memory address is generated according to the
information in the internal memory
7-50
registers and where the
TCB DP
registers.
DP
registers.
registers.
and registers. This allows efficient data transfers
DP
s. Each
TCB TCB
fields.
register. (See "DMA Channel Control" on
TCB
fields in the
TY TCBx DP
bit is set in either one of the
PR
bit is set in either one of the
INT
bit is set in either one of
DRQ
s of channel 1, the
TCB
register is loaded according to the
register, where both
TCB
ADSP-TS101 TigerSHARC Processor
field in each one
LEN
registers are
field of
TY
s' regis-
TCB DP
CHTG
registers
TCB
Hardware Reference