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DSP Architecture
Integer Arithmetic Logic Unit (IALU)
The IALUs can execute standard standalone ALU operations on IALU
register files. The IALUs also provide memory addresses when data is
transferred between memory and registers. The DSP has dual IALUs (the
J-IALU and the K-IALU) that enable simultaneous addresses for multiple
operand reads or writes. The IALUs allow computational operations to
execute with maximum efficiency because the computation units can be
devoted exclusively to processing data.
Each IALU has a multiport, 32-word register file. Operations in the IALU
are not pipelined. The IALUs support pre-modify with no update and
post-modify with update address generation. Circular data buffers are
implemented in hardware. The IALUs support the following types of
instructions:
• Regular IALU instructions
• Move Data instructions
• Load Data instructions
• Load/Store instructions with register update
• Load/Store instructions with immediate update
For indirect addressing (instructions with update), one of the registers in
the register file can be modified by another register in the file or by an
immediate 8- or 32-bit value, either before (pre-modify) or after (post-
modify) the access. For circular buffer addressing, a length value can be
associated with the first four registers to perform automatic modulo
addressing for circular data buffers; the circular buffers can be located at
arbitrary boundaries in memory. Circular buffers allow efficient imple-
mentation of delay lines and other data structures, which are commonly
used in digital filters and Fourier transformations. The TigerSHARC pro-
cessor circular buffers automatically handle address pointer wraparounds,
reducing overhead and simplifying implementation.
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ADSP-TS101 TigerSHARC Processor
Hardware Reference
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