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Table 5-3. Multiprocessing I/O Pins (Cont'd)
Signal
Description
Core Priority Access
CPA
Asserted while the TigerSHARC processor's core accesses external memory. This pin
allows a slave TigerSHARC processor to interrupt a master TigerSHARC processor's
background DMA transfers and gain control of the external bus for core-initiated trans-
actions.
CPA
has an internal 500 Ω pull-up resistor, which is only enabled on the TigerSHARC pro-
cessor with
nection. If
DMA Priority Access
DPA
Asserted while a high priority TigerSHARC processor DMA channel accesses external
memory. This pin allows a high priority DMA channel on a slave TigerSHARC proces-
sor, to interrupt transfers of a normal priority DMA channel on a master TigerSHARC
processor and gain control of the external bus for DMA-initiated transactions.
open drain output, connected to all DSPs in the system. The
500Ω pull-up resistor, which is only enabled on the TigerSHARC processor with
= 0. If
ID0
not used, terminate this pin as pull-up.
Back Off
BOFF
A deadlock situation can occur when the host and a TigerSHARC processor try to read
from each other's bus at the same time. When a deadlock occurs, the host can assert
to force the TigerSHARC processor to relinquish the bus before completing the
BOFF
outstanding transaction; but only if the outstanding transaction is to host memory
space (
MSH
Bus Lock Indication
BUSLOCK
Provides an indication that the current bus master has locked the bus.
Bus Master
BM
The current bus master TigerSHARC processor asserts
this is a strap pin. See the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet for
more information.
Multiprocessing ID
ID2-0
Indicates the TigerSHARC processor's ID. From the ID, the TigerSHARC processor
determines its order in a multiprocessor system. These pins also indicate to the Tiger-
SHARC processor which bus request (
, 001 =
BR0
must have a constant value during system operation and can change during reset
ID2-0
only.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
is an open drain output, connected to all DSPs in the system. The
= 0. If
is not used, terminate this pin as either pull-up or no con-
ID2-0
ID0
is not used, terminate this pin as pull-up.
ID7-1
is not used, terminate this pin as either pull-up or no connection. If
).
, 010 =
, 011 =
BR1
BR2
. For debugging only. At reset,
BM
) to assert when requesting the bus: 000 =
BR7-0
, 100 =
, 101 =
BR3
BR4
BR5
Cluster Bus
pin
CPA
is an
DPA
pin has an internal
DPA
ID2-0
is
ID7-1
, 110 =
, 111 =
.
BR6
BR7
5-39
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