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Multiprocessing
ing the
CURRENT_BUS_MASTER
TigerSHARC processor is the current master, writing to the semaphore
location can be executed safely.
The system indicates whether or not the bus is locked by the Tiger-
SHARC processor via a
the bus lock indication by way of a bridge to another bus.
There is also support for bus lock in the interrupt mechanism. When the
bus lock bit is set and the TigerSHARC processor gets hold of the bus, a
bus lock interrupt is set. For more information, see "Bus Lock Interrupt"
on page 4-7.
Host Interface
The host interface connects a host to the TigerSHARC processor's exter-
nal bus. When the host is a slave, it uses the same protocol as the
TigerSHARC processor—pipelined or slow device protocol depending on
the host interface configuration specified in the
can access the TigerSHARC processor in the same pipelined protocol as
any other TigerSHARC processor. The host can also access any of the
slaves in the system using its own protocol. There are some slight differ-
ences between the host's behavior and the TigerSHARC processor's
behavior. These differences are detailed below.
When a transaction to any address space (except the host space) follows a
read from the host, the non-host transaction is serialized—for example,
the non-host transaction takes place only after all host transactions have
completely terminated. This is illustrated in Figure 5-23.
5-48
field bit in the
pin. This enables the system to propagate
BUSLOCK
ADSP-TS101 TigerSHARC Processor
register. If the
SYSTAT
register. The host
SYSCON
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