Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 296

External Port DMA
exactly as if the TigerSHARC processor core had requested it—the FIFOs
latch or drive data if the transfer is to or from internal memory. Finally,
the for the DMA channel must be preloaded to generate the external
TCB
memory addresses and word count.
The field in the
TY
field in the same register (where DMA request is enabled) allow the
DRQ
DMA to be driven by the DMA request lines, and the I/O device to be
controlled by the
can interface external memory and external I/O devices in a single cycle.
For more information, see "Flyby Transactions" on page 5-34.
Several TigerSHARC processors in a multiprocessing cluster can share a
signal. The
FLYBY
processor bus master only with a DMA external transfer when the
in its associated
When the I/O device wants to be read, it asserts the
assertion (falling edge) of the
TigerSHARC processor responds by executing a write transaction to
memory and asserts
to select the appropriate data to drive. When the I/O device
FLYBY
requires data from memory, it also asserts
cessor responds by executing a read transaction from memory and asserts
to the I/O device—in this case, the
FLYBY
The I/O device can execute up to 15
SHARC processor executes the first transaction in response to it.
For asynchronous and pipeline transfers see "Flyby Transactions" on
page 5-34.
When requesting an access, the external device pulls
ing edge is detected by the TigerSHARC processor and synchronized to
the processor's clock. In order to be recognized in a particular cycle, the
low transition must meet the setup time specified in the data sheet,
DMARx
otherwise it could take effect in the following cycle.
7-62
register (which is external I/O device) and the
TCB0 DP
and signals. This way, the Bus Interface Unit
FLYBY IOEN
register is driven by the current TigerSHARC
FLYBY
register is defined as external I/O.
TCB DP
DMAR0
to indicate when to drive the data, and asserts
IOEN
DMAR0
signal represents one transaction. The
. The TigerSHARC pro-
DMAR0
signal is inactive.
IOEN
signals before the Tiger-
DMARx
DMARx
ADSP-TS101 TigerSHARC Processor
Hardware Reference
field
TY
signal—each
low—the fall-