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Selecting the SDRAM Page Size (Page Boundary)
The processor's SDRAM controller page boundary bits define the page
size, in number of words, of the SDRAM's banks. The setup of Bits5–4 in
the
register is as follows.
SDRCON
00 = 256 words
01 = 512 words
10 = 1024 words
11 = Reserved
Setting the Refresh Counter Value (Refresh Rate)
Since the clock supplied to the SDRAM can vary, the processor provides a
programmable refresh counter to coordinate the supplied clock rate with
the SDRAM device's required refresh rate. Bits8–7 select between four
different refresh rates calculated with the following equation:
=
f
clockx
cycles
00 = Once every 600 cycles
01 = Once every 900 cycles
10 = Once every 1200 cycles
11 = Once every 2400 cycles
Selecting the Precharge to RAS Delay (t
The t
value (precharge to
RP
ber of system clock cycles (
issues a
command and the time it issues an
PRE
ADSP-TS101 TigerSHARC Processor
Hardware Reference
t
ref
(
×
-------------- -
=
refresh_rate
clock
rows
delay) defines the required delay, in num-
RAS
), between the time the SDRAM controller
SCLK
SDRAM Interface
)
)
RP
command.
ACT
6-25
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