Global Registers-Xstat/Ystat Compute Block Status Registers; Alu Registers; Multiplier Registers; Shifter Registers - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Global Registers—XSTAT/YSTAT
Compute Block Status Registers
and
XSTAT YSTAT
state of the compute block status flags. Every flag is updated when an
instruction belonging to its computation unit is completed. For more
information regarding the
ters" in the ADSP-TS101 TigerSHARC Processor Programming Reference.

ALU Registers

The Parallel Results registers (
for sideways sum instructions. For more information regarding the
registers, see "ALU" in the ADSP-TS101 TigerSHARC Processor Program-
ming Reference.

Multiplier Registers

The Multiplier Results registers (
for the different types of fixed-point Multiply-Accumulate instructions.
For more information regarding the
ADSP-TS101 TigerSHARC Processor Programming Reference. These regis-
ters are accessed by different multiplier instructions.

Shifter Registers

The Bit FIFO Overflow register (
instruction. For more information regarding the
PUTBITS
see the
PUTBITS
Programming Reference.

Communications Logic Unit (CLU) Registers

The CLU instructions use 16 Trellis (
is 32 bits wide.
The Trellis history registers (
ADSP-TS101 TigerSHARC Processor
Hardware Reference
are 32-bit compute block status registers that record the
/
X YSTAT
PR0
MR3–0
BFOTMP
instruction in the ADSP-TS101 TigerSHARC Processor
THR1–0)
Memory and Register Map
registers, see "Compute Block Regis-
and ) are two 32-bit registers used
PR1
and ) are used as accumulators
MR4
registers, see "Multiplier" in the
MR
X
) is a 64-bit register used in the
) data registers. Each register
TR15–0
are 32-bit registers.
PR
X
register,
BFOTMP
2-13