Initial Value .......................................................................... 5-15
TigerSHARC Pipelined Interface ................................................ 5-15
Control Signals ..................................................................... 5-16
Basic Transaction .................................................................. 5-16
Wait Cycles ........................................................................... 5-23
Slow Device Protocol .................................................................. 5-27
EPROM Interface ....................................................................... 5-31
Flyby Transactions ...................................................................... 5-34
Multiprocessing .......................................................................... 5-38
DMA Priority Access (DPA) ............................................. 5-43
Bus Fairness - BMAX ..................................................... 5-47
Bus Lock .......................................................................... 5-47
Host Interface ....................................................................... 5-48
Backoff ............................................................................. 5-50
SDRAM INTERFACE
SDRAM I/O Pins ......................................................................... 6-7
Internal TigerSHARC processor Address and SDRAM Physical
Connection ........................................................................ 6-11
SDRAM Programming ............................................................... 6-19
SDRAM Control Register (SDRCON) .................................. 6-19
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ADSP-TS101 TigerSHARC Processor
Hardware Reference
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