Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 308

Link Architecture
Table 8-3. Link Port Register – Group 0x27
Register Register
Number Quads
Reg 0x0
LCTL0
Reg 0x1
LCTL1
Reg 0x2
LCTL2
Reg 0x3
LCTL3
Reg 0x10
LSTAT0
Reg 0x11
LSTAT1
Reg 0x12
LSTAT2
Reg 0x13
LSTAT3
Reg 0x18
LSTATC0
Reg 0x19
LSTATC1
Reg 0x1A
LSTATC2
Reg 0x1B
LSTATC3
The link port issues a DMA request to the transmit DMA channel when
the register is empty and the DMA channel is enabled. The link
LBUFTx
port issues a DMA request to the receive link DMA channel when it
receives a data quad-word—that is, when the
the DMA channel is enabled.
!
If the transmit buffer is empty (for transmit channel) or if the
receive buffer is full (for receive channel), a DMA request is issued
as soon as a link DMA channel (transmit or receive) becomes
active.
8-6
Reserved for Control Registers
and Links 4-5 Registers
Link # 0 control register
Link # 1 control register
Link # 2 control register
Link # 3 control register
Link # 0 status register
Link # 1 status register
Link # 2 status register
Link # 3 status register
Link # 0 status clear register
Link # 1 status clear register
Link # 2 status clear register
Link # 3 status clear register
ADSP-TS101 TigerSHARC Processor
Direct Remarks
Memory
Address
0x1804E0 Reset value
0x400 (
0x1804E1 Reset value
0x400 (
0x1804E2 Reset value
0x400 (
0x1804E3 Reset value
0x400 (
0x1804F0 Read only
0x1804F1 Read only
0x1804F2 Read only
0x1804F3 Read only
0x1804F8 Read only
0x1804F9 Read only
0x1804FA Read only
0x1804FB Read only
register is full and
LBUFRx
Hardware Reference
=1)
LREN
=1)
LREN
=1)
LREN
=1)
LREN