Buslk System Control - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Register Access Features

BUSLK System Control

The register defines the bus lock status. The initial value of the
BUSLK
register after reset is zero.
BUSLK
Reserved
Figure 2-14. BUSLK (Upper) Register Bit Descriptions
The bit descriptions for this register are shown in Figure 2-14 on
page 2-38 and Figure 2-15 on page 2-39.
2-38
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits15 to 1 continued on
Figure 2-15
ADSP-TS101 TigerSHARC Processor
Hardware Reference