Transfer Control Blocks And Chain Loading - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Transfer Control Blocks and Chain Loading

During chain loading, the DMA channel
TCB
values retrieved from internal memory. The
tive locations of an aligned quad-word.
The for each DMA channel can be loaded under core control by exe-
TCB
cuting a quad-word memory read instruction to the DMA
The can also be loaded through chaining or by an external direct
TCB
write. For transfers between internal and external memories, two
must be loaded.
chain loading is requested like all other DMA operations. A
TCB
ing request is latched and held in the DMA controller until it becomes the
highest priority request. If multiple chaining requests are present, the
highest priority DMA channel is dealt with first. DMA channel request
priorities are listed in Table 7-3 on page 7-38.
Setting Up and Starting the Chain
To set up and initiate a chain of DMA operations, the program should
establish this sequence:
• Set up all
• Write to the appropriate DMA control register
( register
TCBx
• Set the
• Define the
• Define the
TCB
ADSP-TS101 TigerSHARC Processor
Hardware Reference
s in internal memory
TCB
):
DP
(chaining enable) bit
CHEN
(channel target)
CHTG
(chaining pointer) fields, noting that the
CHPT
's address is four times the value of this field
Direct Memory Access
registers are loaded with
TCB
is stored in four consecu-
TCB
TCB
registers.
s
TCB
load-
TCB
7-43