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Software Exceptions
• Illegal misalignment of load – not DAB accessible due to odd
address for long-word; or address that is not quad-aligned for
quad-word
• Protection violation – access to a supervisor register in user mode
• Two instructions in the same line with one destination
• More than three results in a single compute instruction line (for
example, add and subtract, multiply, shift)
• Two 32-bit immediate instructions in the same line
• More than one branch in the same aligned quad-word with predic-
tion bit set
Emulation Debug
The vector register is:
•
, no register – after emulation debug exception the Tiger-
IVDBG
SHARC processor fetches from
The emulation debug exception causes the TigerSHARC processor to go
into emulation mode. In this mode, instructions are read from the JTAG
interface and executed in a single step. Emulation mode can be caused by:
• An
EMUTRAP
• A watchpoint match (when programmed to cause an emulation
trap)
• A JTAG emulation activation
During and after reset, the emulation trap is enabled.
4-10
instruction
ADSP-TS101 TigerSHARC Processor
.
EMUIR
Hardware Reference
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