Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 168

Slow Device Protocol
BASIC
SCLK
ADDR
DATA
MS1-0
WR
Figure 5-13. Slow Protocol Write With Wait Cycles
In slow device protocol, wait cycles can be inserted as required. The
register includes a field for the number of internal wait cycles—
SYSCON
between zero and three. Figure 5-13 on page 5-30 and Figure 5-14 on
page 5-31 illustrate slow transactions with one or more wait cycles. This
situation is similar to the zero-wait-state transaction, but the second cycle
(one cycle after the memory select is asserted) is repeated according to the
number of internal wait cycles.
External wait cycles can be inserted by deasserting the
only be done when at least one internal wait state has been configured. To
insert external wait cycles, the
more before the last wait cycle. The extra wait cycles are repeated until one
cycle after the
for an example.
5-30
ACK
signal has been asserted. See Figure 5-15 on page 5-32
ACK
INT WAI T
DATA
CYCLES
signal must be deasserted one cycle or
ADSP-TS101 TigerSHARC Processor
signal. This can
ACK
Hardware Reference