Cycle Counter (Ccnt1–0) - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Cycle Counter (CCNT1–0)
counts cycles while the program is executing. All cycles are
CCNT1–0
counted. The cycle counter is a 64-bit counter that increments with every
cycle, including executions in both user and supervisor modes. All hold,
wait state, aborted instructions, and other delay cycles are also counted.
When the TigerSHARC processor enters emulator mode, the cycle
counter halts, since it is irrelevant.
Performance Monitor Mask – PRFM
The Performance Monitor Mask is a 32-bit register that defines the events
that are monitored by the performance counters. Every bit in the Perfor-
mance Monitor refers to an event that reflects the application performance
(for example, the number of stall cycles in the system). See "Performance
Monitor Mask – PRFM" on page 2-23.
When only one bit in the
bit is counted while the TigerSHARC processor is running in user and
supervisor mode. The count is halted when the TigerSHARC processor is
in emulation mode. For certain events (for example, compute block
instructions or bus transactions), the counter may compute more than one
transaction/instruction every cycle, according to the event occurrence.
When more than one bit is set in the mask, the count is according to the
bit (Bit 31). If the
SUM
formance Mask is set,
occurs. The counter, however, does not sum the events but ORs them. If
the bit is set, the events are summed. In this case, on a cycle where the
SUM
compute block (X or Y) executes two instructions, the counter is incre-
mented by two, and on bus transactions (Bits14–12) the counter could be
incremented by three.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
register is set, the feature indicated by this
PRFM
bit is clear, and more than one bit in the Per-
SUM
counts every cycle where one of the events
CCNT1–0
Debug Functionality
9-11