Sdram Physical Connection - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

SDRAM Physical Connection

Table 6-1. SDRAM I/O Pins (Cont'd)
Signal Description
High Word SDRAM Data Mask
HDQM
When
DQ buffers.
inactive on read transactions. On write transactions,
an even address in word accesses or is active when memory is configured for a
32-bit bus to disable the write of the high word.
SDRAM Write Enable
SDWE
When sampled low while
When sampled high while
other SDRAM accesses,
SDRAM specification.
SDRAM Clock Enable
SDCKE
This pin activates the SDRAM clock for SDRAM self-refresh or suspend modes. A
slave TigerSHARC processor in a multiprocessor system does not have the pull-up
or pull-down. A master TigerSHARC processor (or ID = 0 in a single processor
system) has a 100 kW pull-up before granting the bus to the host, except when the
SDRAM is put in self-refresh mode. In self-refresh mode, the master has a 100 kW
pull-down before granting the bus to the host.
SDA10 SDRAM Address Bit10
Separate A10 signals enable SDRAM refresh operation while the TigerSHARC
processor executes non-SDRAM transactions.
SDRAM Physical Connection
The SDRAM address and data pins can be connected directly to the Tig-
erSHARC processor address and data pins. The data bus is either the full
64 bits or the bottom 32 bits according to the memory bus width pro-
gramming in
SYSCON
6-8
is sampled high, the TigerSHARC processor three-states the SDRAM
HDQM
is valid on SDRAM transactions when
HDQM
is active,
CAS
CAS
defines the type of operation to execute according to
SDWE
(see "SYSCON Programming" on page 5-11). The
HDQM
indicates an SDRAM write access.
SDWE
is active, indicates an SDRAM read access. In
SDWE
ADSP-TS101 TigerSHARC Processor
is asserted and is
CAS
is active when accessing
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