Bus Fairness — Bmax - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Bus Fairness — BMAX
The system designer may want to limit the time a single TigerSHARC
processor holds the bus, in order to prevent bus starvation of other masters
in the system. The
processor may own the bus. The time is defined in
counter is initiated to the defined value when the TigerSHARC processor
gets hold of the bus and starts counting down. Countdown is paused while
the host gets
HBG
not included as a part of the specific TigerSHARC processor share in the
bus. When the
asserted by another TigerSHARC processor in the system, the master Tig-
erSHARC processor relinquishes the bus for at least one cycle. If no other
bus request is asserted, the
ues to own the bus.
The count is not precise. Due to synchronization between clock
BMAX
domains, there may be a skew of up to three
cycles in the period. Additionally, when the
not relinquished until the current transaction has been completed. When
the bus lock (
BUSLK
ignored until the bus lock is cleared. Once it is cleared, the bus is
relinquished.
Bus Lock
The bus lock feature is implemented in order to support atomic
read-modify-write operations. When a TigerSHARC processor needs to
access a semaphore, it requests a bus lock by setting its
register (see "BUSLK System Control" on page 2-38). Setting this
BUSLK
bit causes the bus arbitration logic to request the bus; and maintains
assertion as long as the
tration resumes the regular path. Before accessing a semaphore, the
TigerSHARC processor should check whether it is the bus master by read-
ADSP-TS101 TigerSHARC Processor
Hardware Reference
register defines the period that the TigerSHARC
BMAX
, so the amount of time that the host is the bus master is
count expires and there is another bus request
BMAX
counter is reloaded and the master contin-
BMAX
) bit in the
BUSLK
bit is set. Once the
BUSLK
CCLK
cycles plus three
LCLK
count expires, the bus is
BMAX
register is set, the
BMAX
BUSLK
BUSLK
Cluster Bus
cycles. The
BMAX
SCLK
expire is
bit in the
BR
bit is cleared, arbi-
5-47