Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 6

Broadcast Transfer ............................................................ 2-11
Unmapped Compute Block Registers ................................ 2-12
Global Registers-XSTAT/YSTAT
Compute Block Status Registers ................................. 2-13
ALU Registers .............................................................. 2-13
Multiplier Registers ...................................................... 2-13
Shifter Registers ............................................................ 2-13
Communications Logic Unit (CLU) Registers ............... 2-13
IALU Registers ...................................................................... 2-14
Register J31 - JSTAT ........................................................ 2-15
Register K31 - KSTAT ..................................................... 2-15
Sequencer Register Groups .................................................... 2-15
Sequencer Control Register - SQCTL ............................... 2-16
Sequencer Control Register Set Bits - SQCTLST .............. 2-16
Sequencer Control Register Clear Bits - SQCTLCL .......... 2-16
Sequencer Status Register - SQSTAT ................................ 2-16
SFREG Register ............................................................... 2-16
ILAT Registers .................................................................. 2-19
IMASK Register ............................................................... 2-19
PMASK Register ............................................................... 2-19
Interrupt Vector Table Register Groups ............................. 2-20
Debug Register Groups ......................................................... 2-21
Performance Monitor Counter - PRFCNT ....................... 2-23
Performance Monitor Mask - PRFM ................................ 2-23
Watchpoint Control - WP0CTL, WP1CTL and WP2CTL 2-25
vi ADSP-TS101 TigerSHARC Processor
Hardware Reference