Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 170

EPROM Interface
BASI C
SCLK
ADDR
DATA
WR
DATA
RD
MS1-0/H
RD/WR
ACK
Figure 5-15. Slow Protocol Read/Write With External Wait Cycles
The TigerSHARC processor uses 16 wait cycles for each read access from
the EPROM. During the boot process, the
CS pin until completion.
5-32
INT LAST INT
WAIT WAIT
CYCLES CYCLE CYCLES
EXTERNAL WAIT
CYCLES COUNT
ADSP-TS101 TigerSHARC Processor
EXT LAST EXT
WAI T WAIT
CYCLE
pin is used as the EPROM
BMS
Hardware Reference
DATA