Ending A Dma Sequence - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

• Chaining is enabled, the DMA request bit is set, and a DMA
request input transitions from high to low. Once the block transfer
is completed,
and the DMA starts a new DMA sequence.
• Chaining is enabled and the DMA request bit is reset. Once the
block transfer is completed,
registers occurs and the DMA starts a new DMA sequence.
To start a new DMA sequence after the current one is finished, the pro-
gram must write new parameters to the
!
Writing an active
error interrupt.

Ending a DMA Sequence

A DMA sequence ends when one of the following occurs:
• A channel is disabled by resetting the
registers.
DP
• The count registers decrement to zero and chaining ends.
Suspending a DMA Sequence
A DMA sequence is suspended when the pause bit in one of the
isters is set. (See "DCNTST Register" on page 7-28.)
Resuming a DMA Sequence
A DMA sequence is resumed when the pause bit in one of the
ters is reset. (See "DCNTCL Register" on page 7-28.)
Whenever the DMA request goes low again, the DMA sequence continues
from where it left off.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
chain loading of the channel
TCB
TCB
to an active
TCB
Direct Memory Access
TCB
chain loading of the channel
registers.
TCB
register causes a hardware
TCB
field in one of the
TY
registers occurs
TCB
and
TCB
reg-
DCNT
regis-
DCNT
7-49