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• If there is an SDRAM write to the same page,
issued and the write begins after a delay of
contention on the data bus.
• If there is an SDRAM access to another page,
issued and then, following the
charge (
Different examples of
page 6-36 through Figure 6-8 on page 6-37.
Table 6-14. Pin State During Read Command
Pin
MSSD
CAS
RAS
SDWE
SDCKE
ADSP-TS101 TigerSHARC Processor
Hardware Reference
) and Bank Active
PRE
sequences are shown in Figure 6-7 on
Read
State
low
low
low
high
high
SDRAM Interface
Bstop
latency to prevent
CAS
Bstop
-to-precharge (t
RAS
cycles are issued.
ACT
command is
command is
) delay, Pre-
RP
6-35
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