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TS#0ISTHE
MASTER
SCLK
BR0
BR1
BR2
CPA
HBR
HBG
Figure 5-22. External Bus Arbitration Sequence; More Than One Active
;
Active
CPA
HBR
When a priority access (
being requested – there are two idle cycles for the previous master (that
was interrupted) to gain control of the bus. One cycle is to sense that the
priority access is over, the second is to take control of the bus. This is
illustrated in Figure 5-22 on page 5-45.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
TURN
OVER
HOST IS THE
CYCLE
MASTER
BYTIGERSHARC #1AND #2
or
) finishes, and no other priority access is
CPA
DPA
TURN
OVER
TS#1 ISTHE
CYCLE
MASTER
Cluster Bus
TURN
OVER
TS#2 IS THE
CYCLE
MASTER
5-45
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