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JTAG Functionality
The data registers are:
• Bypass
A IEEE 1149.1 required register, this is a one (1) bit register.
• Boundary
Registers used by multiple JTAG instructions. All four of the
JTAG instructions that use the boundary are required by the IEEE
1149.1 specification.
• EMUIR
The JTAG instruction loads 48 bits, of which the 32 LSBs are
loaded into the
emulation mode the register is loaded four times in a sequence
(with the same JTAG instruction); and each time the data is loaded
into the next word in
Bits63–32 are loaded, and so on.
!
Writing to
lator mode is an illegal operation.
When the four
were loaded to the JTAG are fed into the sequencer and executed.
When a quad-word is loaded into
more full instruction lines. The instruction line must not continue
to the next quad-word. In this case the last slots have to be filled
with "no operation" (NOP) instructions. Except for the restriction
of not crossing the quad-word boundary, this is similar to the
assembler coding described in "Instruction Set" in the
ADSP-TS101 TigerSHARC Processor Programming Reference.
9-16
register. The
EMUIR
—Bits31–0 are loaded first, next
EMUIR
when the TigerSHARC processor is not in emu-
EMUIR
loads have completed, the instructions that
EMUIR
ADSP-TS101 TigerSHARC Processor
is a 128-bit register. In
EMUIR
, it should include one or
EMUIR
Hardware Reference
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