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SDRAM Controller Commands
Read Command
A
command is preceded by an
Read
the page. In
Read
asserted to enable the SDRAM to latch the column address according to
which burst start address is set.
The delay between
parameter. Data is available after the t
met.
Single transactions take a different number of cycles according to transac-
tion size and external bus width.
• Single-word read – 1 cycle
• Long read on 64-bit bus – 1 cycle
• Long read on 32-bit bus – 2 cycles
• Quad read on 64-bit bus – 2 cycles
• Quad read on 32-bit bus – 4 cycles
If no new command is issued to the SDRAM after a
TigerSHARC processor continues reading from the sequential addresses.
This is called "page mode" or "burst". If the whole transaction is more
than one cycle (for example, quad transactions on a 32-bit bus), no new
command is issued to the SDRAM and the rest of the data is read from
sequential addresses. When the whole transaction is completed, the
SDRAM can continue in different ways:
• If there is no new SDRAM transaction, the
issued followed by a precharge command closing the active page.
• If there is an SDRAM read transaction to the same page, a new
cycle begins in the next cycle.
6-34
ACT
commands,
is deasserted and
SDWE
and
commands is determined by the t
ACT
Read
ADSP-TS101 TigerSHARC Processor
command if it is the first access to
CAS
and
latency requirements are
CAS
RCD
Read
Bstop
Hardware Reference
and
are
MSSD
RCD
command, the
command is
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