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Other Interrupt Registers
application can clear a pending interrupt before it is executed. Such an
operation is very sensitive, and it should be executed under these
conditions:
• Non-implemented bits may not be set. When writing to either set
or clear address, the reserved bits must be zero.
• Exception and emulation exception (Bits 62 and 63) may not be
set. In order to cause an exception, use a
to cause an emulation exception, use an
• Interrupts that are level-triggered should not be changed—link
interrupts, hardware error interrupts, or
be level-triggered.
• Writes to
• An interrupt should be cleared while it is masked, otherwise it may
be served before it is cleared.
• Like all other sequencer registers, the set and clear addresses are
single-word writes only.
IMASK Register
The
register is a single 64-bit register accessed as two 32-bit regis-
IMASK
ters,
and
IMASKL
individually dedicated to different interrupts. When an interrupt bit is set
in the
register, the corresponding interrupt is only accepted if the
ILAT
corresponding bit is also set in the
of the interrupt bits is identical to those found in the
is a global hardware interrupt enable. When cleared, no interrupts, except
for exception and emulation, are enabled.
4-12
or
should not be attempted.
ILATL
ILATH
. Mask bits (Bit63–61 and Bit59–0) are
IMASKH
IMASK
instruction; in order
TRAP
EMUTRAP
bits if programmed to
IRQ
register. Consequently, the order
ILAT
ADSP-TS101 TigerSHARC Processor
Hardware Reference
instruction.
register. Bit60
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