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By asserting a
DMARx
be performed by the TigerSHARC processor, an I/O device can transfer
data to TigerSHARC processor internal memory or links. Any flyby out-
put can be used to transfer data between an I/O device and external
memory—in this case, the TigerSHARC processor performs a bus transac-
tion but does not read or write data. "Handshake Mode" on page 7-61
provides additional information regarding DMAR I/O.
Terminology
Terms that appear several times in this chapter are defined below.
• External Port Input FIFO (IFIFO)
Refers to the TigerSHARC processor Bus Interface Unit (BIU)
input FIFO. It is used for all externally-supplied data by bus mas-
ters (other TigerSHARC processors or a host processor), direct
writes or external reads. The IFIFO also holds on-chip destination
addresses and data attributes.
• External Port Output FIFO(OFIFO)
Refers to the TigerSHARC processor BIU output FIFO. It is used
for all outgoing external port addresses, data, and transaction con-
trol signals, including DMA transfers to and from external address
space.
• Transfer Control Block (
A quad-word that defines a set of parameters for the DMA
operation.
• DMA
TCB
A quad-word register that contains a Transfer Control Block.
•
chain loading
TCB
ADSP-TS101 TigerSHARC Processor
Hardware Reference
pin and waiting for the appropriate bus transaction to
)
TCB
register
Direct Memory Access
7-13
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