Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 184

Multiprocessing
The host can begin driving the bus in the same cycle or in any cycle after
is sampled asserted. If the host does not drive the bus immediately
HBG
after is sampled asserted, TigerSHARC pull-ups will stabilize bus sig-
HBG
nals in the interim. All signals are sampled on the rising edge of SCLK.
The host must stop driving the bus no later than the same cycle that
deasserted. The host can stop driving the bus in any of the cycles preced-
ing deassertion as well. The host should deassert
HBR
transaction has completed (RD/WR strobes should be deasserted with
- TigerSHARC pull-ups will stabilize bus signals at this point until the
new bus master drives them).
!
In the arbitration process, requesting bus agents with an active
have higher priority over requesting bus agents with an active
This implies that requesting bus agents with an active
their
BR
Once the bus is owned by the TigerSHARC processor with the bus lock,
the bus lock priority is almost the highest in the system. The Tiger-
SHARC processor relinquishes the bus when the
asserted according to the protocol described in "Backoff" on page 5-50.
When bus lock is set, the bus is not relinquished by either a
assertion, nor by the
HBR
!
In an TigerSHARC processor cluster system, when one of the slave
DSPs performs a priority access
cessor that has control of the bus deasserts the bus request line.
Once the priority access is completed, there are two turnover cycles
for the original TigerSHARC processor to regain control of the
bus—one for the TigerSHARC processor to sense the priority
access is done, and another to take control of the bus. This is illus-
trated in Figure 5-22 on page 5-45, which shows only one turnover
cycle. This is because there are two priority accesses being per-
formed. It only takes one turnover cycle to transfer from one
priority to another.
5-46
s upon sensing that a
count expire.
BMAX
HBR
is asserted by other bus agents.
CPA
and
HBR
or , the TigerSHARC pro-
CPA DPA
ADSP-TS101 TigerSHARC Processor
Hardware Reference
is
HBR
only after the last
HBR
CPA
.
DPA
deassert
DPA
pins are
BOFF
, , or a
CPA DPA