Table of Contents
Advertisement
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 2-5. WPxCTL (Lower) Register Bit Descriptions
Watchpoint Status – WP0STAT, WP1STAT and WP2STAT
Each of the three watchpoints has a status register used to indicate its
operation. After reset, the
The bit descriptions for this register are shown in Figure 2-6 on page 2-28
and Figure 2-7 on page 2-29.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Memory and Register Map
OPMODE Operation mode
00 – Watchpoint disabled
01 – Searching for match on address
10 – Searching for match on range
11 – Searching for match outside range
address
BM Bus master
Bit2 – Sequencer (only for watchpoint 0)
Bit3 – J-IALU
Bit4 – K-IALU
Bit5 – DMA - internal address only
Bit6 – BIU - internal address only
Bit7 – Sequencer - real transactions (in
fetch stage)
R Read transactions
W Write transactions
EXTYPE Do on count expiration
00 – No exception
01 – Exception
10 – Emulation trap
11 – Reserved
SSTP Single step bit in
WPOR – Watchpoint OR bit
in
WP1CTL
WPAND – Watchpoint AND bit
in
WP2CTL
Reserved
field is in "watchpoint disabled" (state 00).
EX
WP0CTL
register only
register only
2-27
Advertisement
Table of Contents
