Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 313

The
LxCLKOUT
ter. Data is latched in the receive buffer on the falling and rising edges of
.
LxCLKOUT
LxCLK OUT
LxCLK IN
LxDAT7:0
Figure 8-5. Quad-word Completion and a
New Quad-word Beginning When
The completion of the transfer and the beginning of a new transfer can be
done according to one of two scenarios, according to the
register (enable verification). If the
LCTLx
byte is sent after the last byte in quad-word, on the rising edge. In this
case, the falling edge data is meaningless and the checksum byte is sam-
pled at the
LxCKIN
the next quad-word follows the last byte of the current word.
The , driven by the receiver to the transmitter, is always used as a
LxCLKIN
"wait" indicator and sometimes used as a connectivity check to ensure that
the receiver is getting the current transmission.
When used as a wait indicator,
the transmitter can complete the current quad-word, but it cannot begin a
new quad-word transmission. If there is more data to be transmitted, the
transmitter sets the
by the receiver.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
is used as the synchronization clock, driven by the transmit-
CONNECTIVITY
CHECK
B0 B1 B2 B3 B4
rising edge. If the
LxCLKIN
to low and waits until
LxCLKOUT
NEXT TRANSFER
ACKNOWLEDGE
B15
B5
Bit is Set
VERE
bit is set, the checksum
VERE
bit is cleared, the first byte of
VERE
is driven low. If
LxCLKIN
Link Ports
NEXT TRANSFER
BEGINS
VER — B0 B1
bit in the
VERE
stays low,
LxCLKIN
is driven high
8-11