Scalability And Multiprocessing - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DSP Architecture
Up to four data words from each memory block can be supplied to each
computation unit, meaning that new data is not required on every cycle
thus leaving alternate cycles for I/O to the memories. This is beneficial in
applications with high I/O requirements since it allows the I/O to occur
without degrading core processor performance.

Scalability and Multiprocessing

The TigerSHARC processor, like the related Analog Devices product the
SHARC processor, is designed for multiprocessing applications. The pri-
mary multiprocessing architecture supported is a cluster of up to eight
TigerSHARC processors that share a common bus, a global memory, and
an interface to either a host processor or to other clusters. In large multi-
processing systems, this cluster can be considered an element and
connected in configurations such as torroid, mesh, tree, crossbar, or oth-
ers. The user can provide a personal interconnect method or use the on-
chip communication ports.
The TigerSHARC processor improves on most of the multiprocessing
capabilities of the SHARC processor and enhances the data transfer band-
width. These capabilities include:
• On-chip bus arbitration for glueless multiprocessing
• Globally accessible internal memory and registers
• Semaphore support
• Powerful, in-circuit multiprocessing emulation
1-18 ADSP-TS101 TigerSHARC Processor
Hardware Reference