Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 407

6-8
SYSTAT System Status Register
2-31, 2-41, 4-8
SYSTAT/SYSTATCL
2-31
system
development
1-4
multi-processor 1-6
single-processor 1-4
system architecture 5-1, 5-3–5-10
system clock distribution
illustrated 10-16
system clock see SCLK
System Design 10-1
T
TCB see Transfer Control Block
Technical or Customer Support
-xxii
technical or customer support -xxii
Technical Publications Online or
on the Web -xxiv
technical publications online or on
the web -xxiv
technical support -xxii
Terminating Read/Write Cycles
6-32
Terminology 7-13
test access port (TAP) 10-38
Test Access Port (TAP) controller
9-14
Test Clock (TCK) 9-13
Test Data Input (TDI) 9-13
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Register
enhancements
Test Data Output (TDO) 9-13
Test Mode Select (TMS) 9-13
Test Reset (TRST) 9-13
Timer 0 Output Pin 3-10
Timer Interrupt and FLAG I/O Ex-
amples 10-12
Timer Operations 3-9
Timer Registers 3-9
Timers 1-23, 3-9, 4-4, 10-11
timers 1-23, 3-9–3-10, 4-4, 10-11
interrupts 4-4
Timer 0 2-18, 2-20, 2-21, 3-9,
3-10
Timer 1 2-18, 2-20, 2-21, 3-9
timer interrupt and FLAG I/O
examples 10-12
timer registers 3-9
TMROE Timer 0 expires 3-10
Trace Buffer – TRCB0 to TRCB7
and TRCBPTR 2-29
Transfer Control Block (TCB)
2-43, 2-45, 4-6, 4-8, 5-10, 7-8,
7-10, 7-11, 7-12, 7-13, 7-15–7-23,
7-28, 7-30, 7-32, 7-33, 7-34, 7-35,
7-37, 7-40, 7-41, 7-42, 7-43, 7-45,
7-46, 7-48, 7-49, 7-50, 7-51, 7-51–
7-57, 7-61, 7-62,
10-33, 10-34, 10-35
Transfer Control Block (TCB)
Registers 7-15
Transfer Control Blocks and Chain
Loading 7-43
Transmission Delays 8-15
Transmitter Error Detection 8-18
INDEX
7-63–7-65,
xix