Pmask Register - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

PMASK Register

The register is a single 64-bit register that is accessed as two 32-bit
PMASK
registers,
PMASKL
in bit assignment.
These registers help the hardware track nested interrupts by masking all
interrupts with a lower or equal priority than the interrupt that is cur-
rently being executed. The
implemented and 32 are reserved. When the TigerSHARC processor
begins to service an interrupt, it's bit in
this ISR is active or nested at some level. The most significant set bit in
indicates which interrupt is currently served. The current interrupt
PMASK
bit is cleared once the service is completed, either by
instruction (see "if cond, RTI (ABS)" and "if cond, RDS" in the
RDS
ADSP-TS101 TigerSHARC Processor Programming Reference).
When the
PMASK
ity to the most significant set bit in
equations, the
the bits above the most significant set bit are set and other bits are clear. A
is only a definition and not a register.
PMASK_R
!
The
RETI
instruction of the interrupt service routing. The first instruction
cannot be an instruction that uses its value, such as
ADSP-TS101 TigerSHARC Processor
Hardware Reference
and . This register is identical to the
PMASKH
PMASK
is nonzero, all the interrupts with a lower or equal prior-
is defined as the mask created by
PMASK_R
register is updated only in the E2 pipe stage of the first
is a 64-bit register, of which 32 bits are
is set. Each set bit indicates
PMASK
are disabled by it. For logic
PMASK
Interrupts
register
IMASK
instruction or by
RTI
; that is, all
PMASK
or .
RTI RETI
4-13