Table of Contents
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INDEX
A
About This Document -xx
access
quad data 1-17
Acknowledge (ACK) 5-3, 5-4,
5-16, 5-23, 5-24, 5-27, 5-51
ACS instruction (Add, Compare
and Select) 2-14
see also enhanced communica-
tions registers
Activ (Activate command) 6-35
Activ-to-Pre delay (tRAS) 6-2
Additional Literature -xxii
Additional
Reference
10-2
Address Bus (ADDR) 2-2, 5-1,
5-4, 6-7, 6-9, 6-10
Address Range 7-31
address space 2-2
external memory bank space
2-2, 2-4–2-5
external multiprocessor space
2-2, 2-5–2-6, 2-44
host address space 2-2
internal address space 2-2,
2-6–2-7
addresses
ADSP-TS101 TigerSHARC Processor
Hardware Reference
algorithms
Alignments 7-30
All DSPs Boot In Turn From A
Single EPROM 10-26
ALU Registers 2-13
ALU registers 2-13
Analog Devices products -xxiii
Material
arbitration 1-16
architecture
Architecture and Microarchitec-
ture Overview 5-3
Arithmetic Logic Unit (ALU) 1-9
Arithmetic Logic Unit, See ALU
AutoDMA 2-44, 4-8, 7-8, 7-10,
7-12, 7-14, 7-15, 7-28, 7-30, 7-33,
7-34, 7-37, 7-38, 7-51, 10-37
AutoDMA Register Channel Op-
eration 7-54
indirect 1-12
relative 1-15
digital filters 1-12
FFT 1-13
Fourier transforms 1-12
turbo-code 1-9
Viterbi 1-9
Static Superscalar 1-6, 1-14
system 1-4
i
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