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8 LINK PORTS
The TigerSHARC processor link port is an optional communication
channel. It is intended to be used for point-to-point communications
between TigerSHARC processors in a system, but can be used to interface
to any other device that is designed to work in the same protocol.
There are four link ports on the TigerSHARC processor. Each link port is
an 8-bit data bidirectional half-duplex port with three additional control
pins.
Data is driven and latched on both the rising and falling edge of the link
clock. Each link port can transfer data at the rate of one byte per
cycle, up to 250 MBytes/second. Automatic token switching changes the
direction of transfer.
Transfer control at the core occurs through interrupts or polling. Transfer
control at the DMA occurs through the dedicated DMA channels for
transmit and receive.
DMA chaining is supported and all link ports can be used for booting.
TigerSHARC processor link ports are not compatible with SHARC pro-
cessor link ports.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
CCLK
8-1
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