Table of Contents
Advertisement
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1
1 1 0 0 1 1 1 1 0 0 1 1 1
Bit 16 continued on
Figure 5-3
Figure 5-4. SYSCON (Lower) Register Bit Descriptions
ADSP-TS101 TigerSHARC Processor
Hardware Reference
BANK 0 IDLE BIT
Same definitions as Host bits
BANK 0 INTERVAL WAIT BITS
Same definitions as Host bits
BANK 0 PIPELINE DEPTH BITS
Same definitions as Host bits
BANK 0 SLOW PROTOCOL BIT
Same definitions as Host bits
BANK 1 IDLE BIT
Same definitions as Host bits
BANK 1 INTERVAL WAIT BITS
Same definitions as Host bits
BANK 1 PIPELINE DEPTH BITS
Same definitions as Host bits
BANK 1 SLOW PROTOCOL BIT
Same definitions as Host bits
HOST IDLE BIT
1 – IDLE cycle inserted between
transactions from this bank
0 – No IDLE cycle inserted
HOST INTERVAL WAIT BITS
00 – Zero wait cycle
01 – One wait cycle
10 – Two wait cycles
11 – Three wait cycles
HOST PIPELINE DEPTH BITS
See Figure 5-3
Cluster Bus
5-13
Advertisement
Table of Contents
