Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 174

Flyby Transactions
SCLK
SDCKE
MSSD
RAS
CAS
SDWE
A11-0
I/O
DATA
DQM
DMARx
FLYBY
IOEN
Figure 5-18. Synchronous Burst Write Transfer Followed by Another Burst
Write Transfer
The sequence illustrated in Figure 5-19 applies when:
• Transfer is followed by another burst read transfer from the
SDRAM to I/O device
• Flyby transaction;
5-36
RA0 CA0
QUAD-WORD
DA0
latency = 2; bus width = 64
CAS
ADSP-TS101 TigerSHARC Processor
CB0
QUAD-WORD
DA2 DB0 DB2
Hardware Reference
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