Table of Contents
Advertisement
The
bit may be set in one of the
2DDMA
There is no restriction on count registers in link DMA channels. In all
cases, if a channel is not idle, the
cannot be 0 or 1.
DY_COUNT
Type Setup – Links Transmit (Channels 4 to 7)
For DMA control registers, link transmit channels can be set up as only
one of the following:
• 2 (internal memory)
• 4 (external memory)
Type Setup – Links Receive (Channels 8 to 11)
For DMA control registers, link receive channels can be set up as only one
of the following:
• 1 (link port),
• 2 (internal memory), or
• 4 (external memory)
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Direct Memory Access
s and cleared in the other.
TCB
cannot be zero. If
DX_COUNT
is set,
2DDMA
7-29
Advertisement
Table of Contents
